VLSI Exercises
We have prepared a series of exercises for our VLSI course at ETH Zurich.
Open source vs proprietary tools
Our goal is to deliver this course using entirely open-source tools. However there are still some practical challenges and some parts of the flow are not yet (in our experience) ready for deployment in teaching. As open source alternatives mature, we will be replacing these gradually.
Setup
We use the excellent VM for IIC-OSIC-TOOLS provided by Institute for Integrated Circuits (IIC), Johannes Kepler University (JKU).
If you are using the infrastructure at ETH Zürich, these tools have already been made available.
Schedule
| Exercise | Name | Files | Tools |
|---|---|---|---|
| 1 | Simulation flow | ex1.tar.gz |
Verilator, Siemens/Mentor Questasim |
| 2 | Block diagrams | ex1.tar.gz |
|
| 3 | RTL, understanding/extending Croc | ex1.tar.gz |
Verilator |
| 4 | Synthesis | ex1.tar.gz |
Yosys |
| 5 | Overview of the flow | ex1.tar.gz |
OpenROAD |
| 6 | Floorplanning | ex1.tar.gz |
OpenROAD |
| 7 | Placement / Timing | ex1.tar.gz |
OpenROAD |
| 8 | Understanding clock tree | ex1.tar.gz |
OpenROAD |
| 9 | Routing / Finishing | ex1.tar.gz |
OpenROAD |
| 10 | Power analysis | ex1.tar.gz |
OpenROAD |
| 11 | DRC / LVS | ex1.tar.gz |
Klayout, Siemens/Mentor Calibre |
| 12 | Tetramax / ATPG | ex1.tar.gz |
OpenRoad (inserting scan_chains) Synopsys TestMAX |
| 13 | Preparing plots, Presenting results, Datasheets |
The VLSI pages are part of the open source VLSI design course offered by the Integrated Systems Laboratory of ETH Zürich, by Luca Benini and Frank K. Gürkaynak. See full list of contributors.