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VLSI

LecturesToggle Dropdown

IntroSystemVerilogSynthesisIC ManufacturingStandard cell based designFloorplanningUnderstanding TimingParasitic effects in VLSI DesignBack-end designPower managementTestingPerformance of ICs

ExercisesToggle Dropdown

Simulation flowBlock diagramsRTL, understanding/extending CrocSynthesisOverview of the flowFloorplanningPlacement / TimingUnderstanding clock treeRouting / FinishingPower analysisDRC / LVSTetramax / ATPGPreparing plots, Presenting results

InformationToggle Dropdown

Student ProjectsSystemVerilog naming conventionsCroc SoCFurther informationContributors

ToolsToggle Dropdown

VerilatorYosysOpenROAD

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Open Source VLSI Design

These pages support the VLSI design activities at ETH Zürich relying on mainly open source EDA design tools.

At the moment This page is a trial page for styles.

It will get updated soon

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Image trials

Figure 1: This is an example caption

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Code example

module test (input  logic       data_in_i,
             input  logic       clk_ci,
             input  logic       rst_ni,
             output logic [7:0] output_o);

// body of module 

always_ff (@posedge clk_ci, @negedge rst_ni) begin
  if (rst_ni ==1'b0) begin    //active_low reset 
    output_o = 8'b0;
  end else begin
    output_o = {8{data_in_i}};
  end 
end

endmodule

Student Task 12

• A typical student task

Some inline code always_ff or more prominent press Shift-F

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Some row examples

Learning goals

Example text

Header

Some quick example text to build on the card title and make up the bulk of the card's content.

Uneven distribution

of columns

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The VLSI pages are part of the open source VLSI design course offered by the Integrated Systems Laboratory of ETH Zürich, by Luca Benini and Frank K. Gürkaynak. See full list of contributors.