Exercise - Simulation flow

VLSI

LecturesToggle Dropdown

IntroSystemVerilogSynthesisIC ManufacturingStandard cell based designFloorplanningUnderstanding TimingParasitic effects in VLSI DesignBack-end designPower managementTestingPerformance of ICs

ExercisesToggle Dropdown

Simulation flowBlock diagramsRTL, understanding/extending CrocSynthesisOverview of the flowFloorplanningPlacement / TimingUnderstanding clock treeRouting / FinishingPower analysisDRC / LVSTetramax / ATPGPreparing plots, Presenting results

InformationToggle Dropdown

Student ProjectsSystemVerilog naming conventionsCroc SoCFurther informationContributors

ToolsToggle Dropdown

VerilatorYosysOpenROAD

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Overview

In this exercise, we will explore the practical application of Verilator, a leading open-source tool for hardware simulation. Verilator converts Verilog code into an executable binary. Our focus will be on simulating a digital design and testbench written in SystemVerilog using Verilator’s relatively new support for timing constructs. We will learn:

• how to translate a SystemVerilog design into an executable binary using Verilator.
• how to specify signals to track in the wave and how to run a simulation.
• how to debug the simulation results using wave forms.

About the style

We will use a number of different styles to identify different types of actions as shown below:

Student Task

Parts of the text that have a gray background, like the current paragraph, indicate steps required to complete the exercise.

Actions that require you to select a specific menu will be shown like the following: menu → sub-menu → sub-sub-menu

Whenever there is an option or a tab that can be found in the current view/menu we will use a BUTTON to indicate such an option.

Throughout the exercise you will be asked to enter certain commands using the command-line1.

sh> command to be entered on the Linux command line

Getting Started

Student Task

• Start by copying the example files into your directory by issuing the command

sh > source /home/efcl_004fs24/ex03_simulation/install.sh 
sh > cd ex03_simulation/croc-soc

Starting from this exercise, we are using a small microcontroller design based around the Ibex RISC-V core (CV32E20). This simpler design still captures most of the complexity of Basilisk while cutting down tool runtime to an acceptable level.

Figure 1: Important elements of an OpenROAD window

You are done with this Exercise.

Discuss your experience with assistants and collegues or continue to explore OpenROAD and the provided design on your own.

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The VLSI pages are part of the open source VLSI design course offered by the Integrated Systems Laboratory of ETH Zürich, by Luca Benini and Frank K. Gürkaynak. See full list of contributors.