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Lectures Toggle Dropdown

Intro SystemVerilog Synthesis IC Manufacturing Standard cell based design Floorplanning Understanding Timing Parasitic effects in VLSI Design Back-end design Power management Testing Performance of ICs

Exercises Toggle Dropdown

Simulation flow RTL, understanding/extending Croc Synthesis Block diagrams Overview of the flow Floorplanning Placement / Timing Understanding clock tree Routing / Finishing Power analysis DRC / LVS Tetramax / ATPG Preparing plots, Presenting results

Information Toggle Dropdown

Projects SystemVerilog naming conventions Croc Further information

Tools Toggle Dropdown

Verilator Yosys OpenROAD

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