VLSI Lectures
From Antalya
The VLSI2 lecture at ETH Zürich covers aspects of modern digital IC design supported by VLSI Exercises.
Schedule
| Lecture | Name | Topics | Slides |
|---|---|---|---|
| 1 | Intro | Summary of design flow, cost of IC design, case for open source EDA | ethz_vlsi_lec1.pptx |
| 2 | RTL | Refresher on SystemVerilog, a few words on computer architecture, our example design Croc | ethz_vlsi_lec2.pptx |
| 3 | Netlist | Logic synthesis, standard cells, other macros, refresher on timing | ethz_vlsi_lec1.pptx |
| 4 | ICT | Short summary of IC manufacturing | ethz_vlsi_lec4.pptx |
| 5 | LEF | Standard cell structure, routing layers, parasitics | ethz_vlsi_lec5.pptx |
| 6 | DEF | Floorplan, I/O ring, ESD structures, packaging | ethz_vlsi_lec6.pptx |
| 7 | LIB | Timing, clock trees, corners | ethz_vlsi_lec7.pptx |
| 8 | SDF | Parasitics, extraction, issues in timing, crosstalk, noise margins, supply droop, ground bounce | ethz_vlsi_lec1.pptx |
| 9 | GDS | Placement, routing, chip finishing, DRC/LVS | ethz_vlsi_lec1.pptx |
| 10 | VCD | Power analysis, static vs dynamic power, IR drop, analysis methods, DVFS | ethz_vlsi_lec10.pptx |
| 11 | WGL | Motivation for test, Fault models, ATPG, BIST, JTAG | ethz_vlsi_lec11.pptx |
| 12 | PPA | Reporting power, performance, area properly | ethz_vlsi_lec1.pptx |
The VLSI pages are part of the open source VLSI design course offered by the Integrated Systems Laboratory of ETH Zürich, by Luca Benini and Frank K. Gürkaynak. See full list of contributors.