VLSI

VLSI

LecturesToggle Dropdown

IntroSystemVerilogSynthesisIC ManufacturingStandard cell based designFloorplanningUnderstanding TimingParasitic effects in VLSI DesignBack-end designPower managementTestingPerformance of ICs

ExercisesToggle Dropdown

Simulation flowBlock diagramsRTL, understanding/extending CrocSynthesisOverview of the flowFloorplanningPlacement / TimingUnderstanding clock treeRouting / FinishingPower analysisDRC / LVSTetramax / ATPGPreparing plots, Presenting results

InformationToggle Dropdown

Student ProjectsSystemVerilog naming conventionsCroc SoCFurther informationContributors

ToolsToggle Dropdown

VerilatorYosysOpenROAD

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Open Source VLSI Design

These pages support the VLSI design activities at ETH Zürich relying on mainly open source EDA design tools.

We are in the process of adapting our lecture series using a predominantly open source EDA design flow and an open PDK from IHP.

This is still very much work in progress, target is to finish most of it by February 2025.

You will find lectures and exercises under these pages.

Open source tools used in these exercises

• Verilator
• Yosys
• OpenROAD

Other related information

• Croc a simplified SoC from PULP platform that is being used in all [[VLSI Exercises|exercises]
• SystemVerilog naming conventions
• Information on possible student projects that forms part of the teaching activity
• Further references and links

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The VLSI pages are part of the open source VLSI design course offered by the Integrated Systems Laboratory of ETH Zürich, by Luca Benini and Frank K. Gürkaynak. See full list of contributors.