VLSI Lectures
Synthesis flow, standard cells, memories, drive strengths, basics of timing Steps for IC Design manufacturing, how transistors are made Layers for routing, track width, separation, pitch, standard cell structure, pins Floorplanning, I/O ring, power rings, macros, packages, ESD timing. Setup/hold constraints, prop/cont delay, min/max timing, input output timing, single clock, clock tree, skew, insertion delay, corners Parasitics, extraction, issues in timing, crosstalk, noise margins, supply droop, ground bounce placement/routing, algorithms, filling, antenna, drc, lvs EASTER BREAK Power, dynamic/static, glitches, estimation techniques, DVFS, electromigration, IR Drop Talk about final projects, Q&A Testing, ATPG, need for test, stuck at faults, JTAG, BIST Final lecture: Metrics for a good design, efficiency. What we did not cover, future of IC design, trends/technologies Reserve / Talk about projects
Schedule
| Lecture | Name | Topics | Slides |
|---|---|---|---|
| 1 | Intro | Summary of design flow, cost of IC design, case for open source EDA | ethz_vlsi_lec1.pptx |
| 2 | RTL | Refresher on SystemVerilog, a few words on computer architecture, our example design Croc | ethz_vlsi_lec2.pptx |
| 3 | Netlist | Logic synthesis, standard cells, other macros, refresher on timing | ethz_vlsi_lec1.pptx |
| 4 | ICT | Short summary of IC manufacturing | ethz_vlsi_lec4.pptx |
| 5 | LEF | Summary of design flow, cost of IC design, case for open source EDA | ethz_vlsi_lec1.pptx |
| 6 | Intro | Summary of design flow, cost of IC design, case for open source EDA | ethz_vlsi_lec1.pptx |
| 7 | Intro | Summary of design flow, cost of IC design, case for open source EDA | ethz_vlsi_lec1.pptx |
| 8 | Intro | Summary of design flow, cost of IC design, case for open source EDA | ethz_vlsi_lec1.pptx |
| 9 | Intro | Summary of design flow, cost of IC design, case for open source EDA | ethz_vlsi_lec1.pptx |
| 10 | Intro | Summary of design flow, cost of IC design, case for open source EDA | ethz_vlsi_lec1.pptx |
| 11 | Intro | Summary of design flow, cost of IC design, case for open source EDA | ethz_vlsi_lec1.pptx |
| 12 | Intro | Summary of design flow, cost of IC design, case for open source EDA | ethz_vlsi_lec1.pptx |
| 13 | Intro | Summary of design flow, cost of IC design, case for open source EDA | ethz_vlsi_lec1.pptx |
The VLSI pages are part of the open source VLSI design course offered by the Integrated Systems Laboratory of ETH Zürich, by Luca Benini and Frank K. Gürkaynak. See full list of contributors.