VLSI: Difference between revisions
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We are in the process of adapting our lecture series using a predominantly open source EDA design flow and an open [[PDK]] from [https://github.com/IHP-GmbH/IHP-Open-PDK IHP]. | We are in the process of adapting our lecture series using a predominantly open source EDA design flow and an open [[PDK]] from [https://github.com/IHP-GmbH/IHP-Open-PDK IHP]. This is still very much work in progress, target is to finish most by February 2025. | ||
You will find [[VLSI Lectures|lectures]] and [[VLSI Exercises| exercises]] under these pages. | You will find [[VLSI Lectures|lectures]] and [[VLSI Exercises| exercises]] under these pages. | ||
Revision as of 09:20, 18 August 2024
Open Source VLSI Design
These pages support the VLSI design activities at ETH Zürich relying on mainly open source EDA design tools.
We are in the process of adapting our lecture series using a predominantly open source EDA design flow and an open PDK from IHP. This is still very much work in progress, target is to finish most by February 2025.
You will find lectures and exercises under these pages.
Open source tools used in these exercises
Other related information
- Croc a simplified SoC from PULP platform that is being used in all [[VLSI Exercises|exercises]
- SystemVerilog naming conventions
- Information on possible student projects that forms part of the teaching activity
- Further references and links
The VLSI pages are part of the open source VLSI design course offered by the Integrated Systems Laboratory of ETH Zürich, by Luca Benini and Frank K. Gürkaynak. See full list of contributors.