VLSI: Difference between revisions

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<div class="alert alert-danger" role="alert">
We are in the process of adapting our lecture series using a predominantly open source EDA design flow and an open [[PDK]] from [https://github.com/IHP-GmbH/IHP-Open-PDK IHP].
At the moment This page is a '''trial''' page for styles.  


It will get updated soon
You will find [[VLSI Lectures|lectures]] and [[VLSI Exercises| exercises]] under these pages.
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----
Open source tools used in these exercises
=== Image trials ===
* [[Verilator]]
* [[Yosys]]
* [[OpenROAD]]


{{VLSIfigure|ex2_openroad_croc.png|This is an example caption|1}}
Other related information
----
* [[Croc]] a simplified SoC from  [https://github.com/pulp-platform/croc PULP platform] that is being used in all [[VLSI Exercises|exercises]
===Code example===
* [[SystemVerilog naming conventions]]
<syntaxhighlight lang="verilog">
* [[VLSI Projects|Information on possible student projects]] that forms part of the teaching activity
module test (input  logic      data_in_i,
* [[VLSI Reading| Further references and links]]  
            input  logic      clk_ci,
            input  logic      rst_ni,
            output logic [7:0] output_o);


// body of module


always_ff (@posedge clk_ci, @negedge rst_ni) begin
  if (rst_ni ==1'b0) begin    //active_low reset
    output_o = 8'b0;
  end else begin
    output_o = {8{data_in_i}};
  end
end
endmodule
</syntaxhighlight>
Some inline code <code>always_ff</code> or more prominent press <kbd>Shift-F</kbd>
----
===Some row examples===
<div class="container-fluid">
  <div class="row">
    <div class="col">
      <div class="card">
        <h4 class="card-header">
          Learning goals
      </h4>
      <div class="card-body">
Example text
      </div>
    </div>
    </div>     
    <div class="col">
<div class="card text-white bg-danger mb-3">
  <h5 class="card-header">Header</h5>
  <div class="card-body">
Some quick example text to build on the card title and make up the bulk of the card's content.
  </div>
</div>
    </div>
  </div>
  <div class="row">
    <div class="col-8">
Uneven distribution
    </div>
    <div class="col-4">
of columns
    </div>
  </div>
</div>


{{VLSIfooter}}
{{VLSIfooter}}

Revision as of 09:19, 18 August 2024

VLSI
LecturesToggle Dropdown
IntroSystemVerilogSynthesisIC ManufacturingStandard cell based designFloorplanningUnderstanding TimingParasitic effects in VLSI DesignBack-end designPower managementTestingPerformance of ICs
ExercisesToggle Dropdown
Simulation flowBlock diagramsRTL, understanding/extending CrocSynthesisOverview of the flowFloorplanningPlacement / TimingUnderstanding clock treeRouting / FinishingPower analysisDRC / LVSTetramax / ATPGPreparing plots, Presenting results
InformationToggle Dropdown
Student ProjectsSystemVerilog naming conventionsCroc SoCFurther informationContributors
ToolsToggle Dropdown
VerilatorYosysOpenROAD

    Open Source VLSI Design

    These pages support the VLSI design activities at ETH Zürich relying on mainly open source EDA design tools.

We are in the process of adapting our lecture series using a predominantly open source EDA design flow and an open PDK from IHP.

You will find lectures and exercises under these pages.

Open source tools used in these exercises

Other related information



The VLSI pages are part of the open source VLSI design course offered by the Integrated Systems Laboratory of ETH Zürich, by Luca Benini and Frank K. Gürkaynak. See full list of contributors.

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