VLSI Exercises: Difference between revisions
From Antalya
No edit summary |
No edit summary |
||
| Line 18: | Line 18: | ||
<th scope="col">Name</th> | <th scope="col">Name</th> | ||
<th scope="col">Files</th> | <th scope="col">Files</th> | ||
<th scope="col">Tools</th> | |||
</tr> | </tr> | ||
<tr> | <tr> | ||
| Line 23: | Line 24: | ||
<td>[[Exercise - Simulation flow|Simulation flow]]</td> | <td>[[Exercise - Simulation flow|Simulation flow]]</td> | ||
<td><code>ex1.tar.gz</code></td> | <td><code>ex1.tar.gz</code></td> | ||
<td>[[Verilator]], '''Siemens/Mentor Questasim'''</td> | |||
</tr> | </tr> | ||
<tr> | <tr> | ||
| Line 28: | Line 30: | ||
<td>[[Exercise - RTL, understanding/extending Croc|RTL, understanding/extending Croc]]</td> | <td>[[Exercise - RTL, understanding/extending Croc|RTL, understanding/extending Croc]]</td> | ||
<td><code>ex1.tar.gz</code></td> | <td><code>ex1.tar.gz</code></td> | ||
<td></td> | |||
</tr> | </tr> | ||
<tr> | <tr> | ||
| Line 33: | Line 36: | ||
<td>[[Exercise - Synthesis|Synthesis]]</td> | <td>[[Exercise - Synthesis|Synthesis]]</td> | ||
<td><code>ex1.tar.gz</code></td> | <td><code>ex1.tar.gz</code></td> | ||
<td>[[Yosys]]</td> | |||
</tr> | </tr> | ||
<tr> | <tr> | ||
| Line 38: | Line 42: | ||
<td>[[Exercise - Block diagrams|Block diagrams]]</td> | <td>[[Exercise - Block diagrams|Block diagrams]]</td> | ||
<td><code>ex1.tar.gz</code></td> | <td><code>ex1.tar.gz</code></td> | ||
<td></td> | |||
</tr> | </tr> | ||
<tr> | <tr> | ||
| Line 43: | Line 48: | ||
<td>[[Exercise - Introduction to OpenRoad|Overview of the flow]]</td> | <td>[[Exercise - Introduction to OpenRoad|Overview of the flow]]</td> | ||
<td><code>ex1.tar.gz</code></td> | <td><code>ex1.tar.gz</code></td> | ||
<td>[[OpenROAD]]</td> | |||
</tr> | </tr> | ||
<tr> | <tr> | ||
| Line 48: | Line 54: | ||
<td>[[Exercise - Floorplanning|Floorplanning]]</td> | <td>[[Exercise - Floorplanning|Floorplanning]]</td> | ||
<td><code>ex1.tar.gz</code></td> | <td><code>ex1.tar.gz</code></td> | ||
<td>[[OpenROAD]]</td> | |||
</tr> | </tr> | ||
<tr> | <tr> | ||
| Line 53: | Line 60: | ||
<td>[[Exercise - Placement / Timing|Placement / Timing]]</td> | <td>[[Exercise - Placement / Timing|Placement / Timing]]</td> | ||
<td><code>ex1.tar.gz</code></td> | <td><code>ex1.tar.gz</code></td> | ||
<td>[[OpenROAD]]</td> | |||
</tr> | </tr> | ||
<tr> | <tr> | ||
| Line 58: | Line 66: | ||
<td>[[Exercise - Understanding clock tree|Understanding clock tree]]</td> | <td>[[Exercise - Understanding clock tree|Understanding clock tree]]</td> | ||
<td><code>ex1.tar.gz</code></td> | <td><code>ex1.tar.gz</code></td> | ||
<td>[[OpenROAD]]</td> | |||
</tr> | </tr> | ||
<tr> | <tr> | ||
| Line 63: | Line 72: | ||
<td>[[Exercise - Routing / Finishing|Routing / Finishing]]</td> | <td>[[Exercise - Routing / Finishing|Routing / Finishing]]</td> | ||
<td><code>ex1.tar.gz</code></td> | <td><code>ex1.tar.gz</code></td> | ||
<td>[[OpenROAD]]</td> | |||
</tr> | </tr> | ||
<tr> | <tr> | ||
| Line 68: | Line 78: | ||
<td>[[Exercise - Power analysis|Power analysis ]]</td> | <td>[[Exercise - Power analysis|Power analysis ]]</td> | ||
<td><code>ex1.tar.gz</code></td> | <td><code>ex1.tar.gz</code></td> | ||
<td>[[OpenROAD]]</td> | |||
</tr> | </tr> | ||
<tr> | <tr> | ||
| Line 73: | Line 84: | ||
<td>[[Exercise - DRC / LVS|DRC / LVS]]</td> | <td>[[Exercise - DRC / LVS|DRC / LVS]]</td> | ||
<td><code>ex1.tar.gz</code></td> | <td><code>ex1.tar.gz</code></td> | ||
<td>[[Klayout]], '''Siemens/Mentor Calibre'''</td> | |||
</tr> | </tr> | ||
<tr> | <tr> | ||
| Line 78: | Line 90: | ||
<td>[[Exercise - Tetramax / ATPG|Tetramax / ATPG]]</td> | <td>[[Exercise - Tetramax / ATPG|Tetramax / ATPG]]</td> | ||
<td><code>ex1.tar.gz</code></td> | <td><code>ex1.tar.gz</code></td> | ||
<td>'''Synopsys TestMAX'''</td> | |||
</tr> | </tr> | ||
<tr> | <tr> | ||
<th scope="row">13</th> | <th scope="row">13</th> | ||
<td>[[Exercise - Preparing plots, Presenting results|Preparing plots, Presenting results]]</td> | <td>[[Exercise - Preparing plots, Presenting results|Preparing plots, Presenting results]]</td> | ||
<td | <td></td> | ||
</tr> | </tr> | ||
</table> | </table> | ||
Revision as of 05:53, 9 August 2024
We have prepared a series of exercises for our VLSI course at ETH Zurich.
Open source vs proprietary tools
Our goal is to deliver this course using entirely open-source tools. However there are still some practical challenges and some parts of the flow are not yet (in our experience) ready for deployment in teaching. As open source alternatives mature, we will be replacing these gradually.
Setup
We use the excellent VM for IIC-OSIC-TOOLS provided by Institute for Integrated Circuits (IIC), Johannes Kepler University (JKU).
If you are using the infrastructure at ETH Zürich, these tools have already been made available.
Schedule
| Exercise | Name | Files | Tools |
|---|---|---|---|
| 1 | Simulation flow | ex1.tar.gz |
Verilator, Siemens/Mentor Questasim |
| 2 | RTL, understanding/extending Croc | ex1.tar.gz |
|
| 3 | Synthesis | ex1.tar.gz |
Yosys |
| 4 | Block diagrams | ex1.tar.gz |
|
| 5 | Overview of the flow | ex1.tar.gz |
OpenROAD |
| 6 | Floorplanning | ex1.tar.gz |
OpenROAD |
| 7 | Placement / Timing | ex1.tar.gz |
OpenROAD |
| 8 | Understanding clock tree | ex1.tar.gz |
OpenROAD |
| 9 | Routing / Finishing | ex1.tar.gz |
OpenROAD |
| 10 | Power analysis | ex1.tar.gz |
OpenROAD |
| 11 | DRC / LVS | ex1.tar.gz |
Klayout, Siemens/Mentor Calibre |
| 12 | Tetramax / ATPG | ex1.tar.gz |
Synopsys TestMAX |
| 13 | Preparing plots, Presenting results |
The VLSI pages are part of the open source VLSI design course offered by the Integrated Systems Laboratory of ETH Zürich, by Luca Benini and Frank K. Gürkaynak. See full list of contributors.