VLSI Exercises: Difference between revisions
(Created page with "{{VLSInavbar}} We have prepared a series of exercises for our VLSI course at [https://www.ethz.ch ETH Zurich]. === What is needed === VM === Schedule === <table class="table"> <tr> <th scope="col">Exercise</th> <th scope="col">Name</th> <th scope="col">Files</th> </tr> <tr> <th scope="row">1</th> <td>Simulation flow</td> <td><code>ex1.tar.gz</code></td> </tr> <tr> <th scope="...") |
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We have prepared a series of exercises for our VLSI course at [https://www.ethz.ch ETH Zurich]. | We have prepared a series of exercises for our VLSI course at [https://www.ethz.ch ETH Zurich]. | ||
=== | === Open source vs proprietary tools === | ||
VM | Our goal is to deliver this course using ''entirely'' open-source tools. However there are still some practical challenges and some parts of the flow are not yet (''in our experience'') ready for deployment in teaching. As open source alternatives mature, we will be replacing these gradually. | ||
=== Setup === | |||
We use the excellent VM [https://github.com/iic-jku/IIC-OSIC-TOOLS] provided by [https://iic.jku.at/ Institute for Integrated Circuits (IIC), Johannes Kepler University (JKU)]. | |||
<div class="alert alert-danger" role="alert"> | |||
If you are using the infrastructure at ETH Zürich, these tools have already been made available. | |||
</div> | |||
=== Schedule === | === Schedule === | ||
Revision as of 05:46, 9 August 2024
We have prepared a series of exercises for our VLSI course at ETH Zurich.
Open source vs proprietary tools
Our goal is to deliver this course using entirely open-source tools. However there are still some practical challenges and some parts of the flow are not yet (in our experience) ready for deployment in teaching. As open source alternatives mature, we will be replacing these gradually.
Setup
We use the excellent VM [1] provided by Institute for Integrated Circuits (IIC), Johannes Kepler University (JKU).
If you are using the infrastructure at ETH Zürich, these tools have already been made available.
Schedule
| Exercise | Name | Files |
|---|---|---|
| 1 | Simulation flow | ex1.tar.gz |
| 2 | RTL, understanding/extending Croc | ex1.tar.gz |
| 3 | Synthesis | ex1.tar.gz |
| 4 | Block diagrams | ex1.tar.gz |
| 5 | Overview of the flow | ex1.tar.gz |
| 6 | Floorplanning | ex1.tar.gz |
| 7 | Placement / Timing | ex1.tar.gz |
| 8 | Understanding clock tree | ex1.tar.gz |
| 9 | Routing / Finishing | ex1.tar.gz |
| 10 | Power analysis | ex1.tar.gz |
| 11 | DRC / LVS | ex1.tar.gz |
| 12 | Tetramax / ATPG | ex1.tar.gz |
| 13 | Preparing plots, Presenting results | ex1.tar.gz |
The VLSI pages are part of the open source VLSI design course offered by the Integrated Systems Laboratory of ETH Zürich, by Luca Benini and Frank K. Gürkaynak. See full list of contributors.