Template: VLSInavbar: Difference between revisions
From Antalya
No edit summary |
No edit summary |
||
| Line 3: | Line 3: | ||
VLSI Lectures | Lectures | VLSI Lectures | Lectures | ||
* | * Lecture - Intro|Intro | ||
* | * Lecture - SystemVerilog|SystemVerilog | ||
* | * Lecture - Synthesis|Synthesis | ||
* | * Lecture - IC Manufacturing|IC Manufacturing | ||
* Lecture - Standard cell based design|Standard cell based design | |||
* Lecture - Floorplanning|Floorplanning | |||
* Lecture - Understanding Timing|Understanding Timing | |||
* Lecture - Parasitic effects in VLSI Design|Parasitic effects in VLSI Design | |||
* Lecture - Back-end design|Back-end design | |||
* Lecture - Power management|Power management | |||
* Lecture - Testing|Testing | |||
* Lecture - Performance of ICs|Performance of ICs | |||
VLSI Exercises | Exercises | VLSI Exercises | Exercises | ||