Template: VLSInavbar: Difference between revisions

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* Exercise - Preparing plots, Presenting results|Preparing plots, Presenting results
* Exercise - Preparing plots, Presenting results|Preparing plots, Presenting results


VLSI Projects | Projects  
VLSI Information | Information
* VLSI Projects | Projects  
* SystemVerilog naming conventions
* Croc
* VLSI Reading | Further information
 
Open source IC Design tools | Tools 
* Verilator
* Yosys
* OpenROAD


About | About VLSI
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[[Category:VLSI]]
[[Category:VLSI]]

Revision as of 05:59, 9 August 2024

VLSI
LecturesToggle Dropdown
OneTwoThreeFour
ExercisesToggle Dropdown
Simulation flowRTL, understanding/extending CrocSynthesisBlock diagramsOverview of the flowFloorplanningPlacement / TimingUnderstanding clock treeRouting / FinishingPower analysisDRC / LVSTetramax / ATPGPreparing plots, Presenting results
InformationToggle Dropdown
ProjectsSystemVerilog naming conventionsCrocFurther information
ToolsToggle Dropdown
VerilatorYosysOpenROAD
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