Template: VLSInavbar: Difference between revisions
From Antalya
No edit summary |
No edit summary |
||
(One intermediate revision by the same user not shown) | |||
Line 18: | Line 18: | ||
VLSI Exercises | Exercises | VLSI Exercises | Exercises | ||
* Exercise - Simulation flow|Simulation flow | * Exercise - Simulation flow|Simulation flow | ||
* Exercise - Block diagrams|Block diagrams | |||
* Exercise - RTL, understanding/extending Croc|RTL, understanding/extending Croc | * Exercise - RTL, understanding/extending Croc|RTL, understanding/extending Croc | ||
* Exercise - Synthesis|Synthesis | * Exercise - Synthesis|Synthesis | ||
* Exercise - Introduction to OpenRoad|Overview of the flow | * Exercise - Introduction to OpenRoad|Overview of the flow | ||
* Exercise - Floorplanning|Floorplanning | * Exercise - Floorplanning|Floorplanning | ||
Line 32: | Line 32: | ||
VLSI Information | Information | VLSI Information | Information | ||
* VLSI Projects | Projects | * VLSI Projects | Student Projects | ||
* SystemVerilog naming conventions | * SystemVerilog naming conventions | ||
* Croc | * Croc |Croc SoC | ||
* VLSI Reading | Further information | * VLSI Reading | Further information | ||
* VLSI Contributors | Contributors | |||
Open source IC Design tools | Tools | Open source IC Design tools | Tools |