VLSI Exercises: Difference between revisions

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(Created page with "{{VLSInavbar}} We have prepared a series of exercises for our VLSI course at [https://www.ethz.ch ETH Zurich]. === What is needed === VM === Schedule === <table class="table"> <tr> <th scope="col">Exercise</th> <th scope="col">Name</th> <th scope="col">Files</th> </tr> <tr> <th scope="row">1</th> <td>Simulation flow</td> <td><code>ex1.tar.gz</code></td> </tr> <tr> <th scope="...")
 
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We have prepared a series of exercises for our VLSI course at [https://www.ethz.ch ETH Zurich].  
We have prepared a series of exercises for our VLSI course at [https://www.ethz.ch ETH Zurich].  


=== What is needed ===  
=== Open source vs proprietary tools ===
VM
Our goal is to deliver this course using ''entirely'' open-source tools. However there are still some practical challenges and some parts of the flow are not yet (''in our experience'') ready for deployment in teaching. As open source alternatives mature, we will be replacing these gradually.
 
=== Setup ===
We use the excellent VM for [https://github.com/iic-jku/IIC-OSIC-TOOLS IIC-OSIC-TOOLS] provided by [https://iic.jku.at/ Institute for Integrated Circuits (IIC), Johannes Kepler University (JKU)].
 
<div class="alert alert-success" role="alert">
If you are using the infrastructure at ETH Zürich, these tools have already been made available. 
</div>


=== Schedule ===  
=== Schedule ===  
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       <th scope="col">Name</th>
       <th scope="col">Name</th>
       <th scope="col">Files</th>
       <th scope="col">Files</th>
      <th scope="col">Tools</th>
     </tr>
     </tr>
   <tr>
   <tr>
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       <td>[[Exercise - Simulation flow|Simulation flow]]</td>
       <td>[[Exercise - Simulation flow|Simulation flow]]</td>
       <td><code>ex1.tar.gz</code></td>
       <td><code>ex1.tar.gz</code></td>
      <td>[[Verilator]], '''Siemens/Mentor Questasim'''</td>
     </tr>
     </tr>
   <tr>
   <tr>
       <th scope="row">2</th>
       <th scope="row">2</th>
       <td>[[Exercise - RTL, understanding/extending Croc|RTL, understanding/extending Croc]]</td>
       <td>[[Exercise - Block diagrams|Block diagrams]]</td>
       <td><code>ex1.tar.gz</code></td>
       <td><code>ex1.tar.gz</code></td>
      <td></td>
     </tr>
     </tr>
   <tr>
   <tr>
       <th scope="row">3</th>
       <th scope="row">3</th>
       <td>[[Exercise - Synthesis|Synthesis]]</td>
       <td>[[Exercise - RTL, understanding/extending Croc|RTL, understanding/extending Croc]]</td>
       <td><code>ex1.tar.gz</code></td>
       <td><code>ex1.tar.gz</code></td>
      <td>[[Verilator]]</td>
     </tr>
     </tr>
   <tr>
   <tr>
       <th scope="row">4</th>
       <th scope="row">4</th>
       <td>[[Exercise - Block diagrams|Block diagrams]]</td>
       <td>[[Exercise - Synthesis|Synthesis]]</td>
       <td><code>ex1.tar.gz</code></td>
       <td><code>ex1.tar.gz</code></td>
      <td>[[Yosys]]</td>
     </tr>
     </tr>
   <tr>
   <tr>
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       <td>[[Exercise - Introduction to OpenRoad|Overview of the flow]]</td>
       <td>[[Exercise - Introduction to OpenRoad|Overview of the flow]]</td>
       <td><code>ex1.tar.gz</code></td>
       <td><code>ex1.tar.gz</code></td>
      <td>[[OpenROAD]]</td>
     </tr>
     </tr>
   <tr>
   <tr>
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       <td>[[Exercise - Floorplanning|Floorplanning]]</td>
       <td>[[Exercise - Floorplanning|Floorplanning]]</td>
       <td><code>ex1.tar.gz</code></td>
       <td><code>ex1.tar.gz</code></td>
      <td>[[OpenROAD]]</td>
     </tr>
     </tr>
   <tr>
   <tr>
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       <td>[[Exercise - Placement / Timing|Placement / Timing]]</td>
       <td>[[Exercise - Placement / Timing|Placement / Timing]]</td>
       <td><code>ex1.tar.gz</code></td>
       <td><code>ex1.tar.gz</code></td>
      <td>[[OpenROAD]]</td>
     </tr>
     </tr>
   <tr>
   <tr>
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       <td>[[Exercise - Understanding clock tree|Understanding clock tree]]</td>
       <td>[[Exercise - Understanding clock tree|Understanding clock tree]]</td>
       <td><code>ex1.tar.gz</code></td>
       <td><code>ex1.tar.gz</code></td>
      <td>[[OpenROAD]]</td>
     </tr>
     </tr>
   <tr>
   <tr>
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       <td>[[Exercise - Routing / Finishing|Routing / Finishing]]</td>
       <td>[[Exercise - Routing / Finishing|Routing / Finishing]]</td>
       <td><code>ex1.tar.gz</code></td>
       <td><code>ex1.tar.gz</code></td>
      <td>[[OpenROAD]]</td>
     </tr>
     </tr>
   <tr>
   <tr>
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       <td>[[Exercise - Power analysis|Power analysis ]]</td>
       <td>[[Exercise - Power analysis|Power analysis ]]</td>
       <td><code>ex1.tar.gz</code></td>
       <td><code>ex1.tar.gz</code></td>
      <td>[[OpenROAD]]</td>
     </tr>
     </tr>
   <tr>
   <tr>
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       <td>[[Exercise - DRC / LVS|DRC / LVS]]</td>
       <td>[[Exercise - DRC / LVS|DRC / LVS]]</td>
       <td><code>ex1.tar.gz</code></td>
       <td><code>ex1.tar.gz</code></td>
      <td>[[Klayout]], '''Siemens/Mentor Calibre'''</td>
     </tr>
     </tr>
   <tr>
   <tr>
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       <td>[[Exercise - Tetramax / ATPG|Tetramax / ATPG]]</td>
       <td>[[Exercise - Tetramax / ATPG|Tetramax / ATPG]]</td>
       <td><code>ex1.tar.gz</code></td>
       <td><code>ex1.tar.gz</code></td>
      <td>[[OpenRoad]] (inserting scan_chains) '''Synopsys TestMAX'''</td>
     </tr>
     </tr>
   <tr>
   <tr>
       <th scope="row">13</th>
       <th scope="row">13</th>
       <td>[[Exercise - Preparing plots, Presenting results|Preparing plots, Presenting results]]</td>
       <td>[[Exercise - Preparing plots, Presenting results|Preparing plots, Presenting results, Datasheets]]</td>
       <td><code>ex1.tar.gz</code></td>
       <td></td>
      <td></td>
     </tr>  
     </tr>  
  </table>
  </table>
 
----






{{VLSIfooter}}
{{VLSIfooter}}

Latest revision as of 07:32, 17 October 2024

VLSI
LecturesToggle Dropdown
IntroSystemVerilogSynthesisIC ManufacturingStandard cell based designFloorplanningUnderstanding TimingParasitic effects in VLSI DesignBack-end designPower managementTestingPerformance of ICs
ExercisesToggle Dropdown
Simulation flowBlock diagramsRTL, understanding/extending CrocSynthesisOverview of the flowFloorplanningPlacement / TimingUnderstanding clock treeRouting / FinishingPower analysisDRC / LVSTetramax / ATPGPreparing plots, Presenting results
InformationToggle Dropdown
Student ProjectsSystemVerilog naming conventionsCroc SoCFurther informationContributors
ToolsToggle Dropdown
VerilatorYosysOpenROAD

We have prepared a series of exercises for our VLSI course at ETH Zurich.

Open source vs proprietary tools

Our goal is to deliver this course using entirely open-source tools. However there are still some practical challenges and some parts of the flow are not yet (in our experience) ready for deployment in teaching. As open source alternatives mature, we will be replacing these gradually.

Setup

We use the excellent VM for IIC-OSIC-TOOLS provided by Institute for Integrated Circuits (IIC), Johannes Kepler University (JKU).

Schedule

Exercise Name Files Tools
1 Simulation flow ex1.tar.gz Verilator, Siemens/Mentor Questasim
2 Block diagrams ex1.tar.gz
3 RTL, understanding/extending Croc ex1.tar.gz Verilator
4 Synthesis ex1.tar.gz Yosys
5 Overview of the flow ex1.tar.gz OpenROAD
6 Floorplanning ex1.tar.gz OpenROAD
7 Placement / Timing ex1.tar.gz OpenROAD
8 Understanding clock tree ex1.tar.gz OpenROAD
9 Routing / Finishing ex1.tar.gz OpenROAD
10 Power analysis ex1.tar.gz OpenROAD
11 DRC / LVS ex1.tar.gz Klayout, Siemens/Mentor Calibre
12 Tetramax / ATPG ex1.tar.gz OpenRoad (inserting scan_chains) Synopsys TestMAX
13 Preparing plots, Presenting results, Datasheets



The VLSI pages are part of the open source VLSI design course offered by the Integrated Systems Laboratory of ETH Zürich, by Luca Benini and Frank K. Gürkaynak. See full list of contributors.

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