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(Created page with "<btn class="btn-primary"> VLSI VLSI Lectures | Lectures * One * Two * Three * Four VLSI Exercises | Exercises * Exercise - Introduction to OpenRoad | Introduction to OpenRoad * Two * Three About | About VLSI </btn> ---- Category:VLSI") |
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VLSI Lectures | Lectures | VLSI Lectures | Lectures | ||
* | * Lecture - Intro|Intro | ||
* | * Lecture - SystemVerilog|SystemVerilog | ||
* | * Lecture - Synthesis|Synthesis | ||
* | * Lecture - IC Manufacturing|IC Manufacturing | ||
* Lecture - Standard cell based design|Standard cell based design | |||
* Lecture - Floorplanning|Floorplanning | |||
* Lecture - Understanding Timing|Understanding Timing | |||
* Lecture - Parasitic effects in VLSI Design|Parasitic effects in VLSI Design | |||
* Lecture - Back-end design|Back-end design | |||
* Lecture - Power management|Power management | |||
* Lecture - Testing|Testing | |||
* Lecture - Performance of ICs|Performance of ICs | |||
VLSI Exercises | Exercises | VLSI Exercises | Exercises | ||
* Exercise - Introduction to OpenRoad | | * Exercise - Simulation flow|Simulation flow | ||
* | * Exercise - Block diagrams|Block diagrams | ||
* | * Exercise - RTL, understanding/extending Croc|RTL, understanding/extending Croc | ||
* Exercise - Synthesis|Synthesis | |||
* Exercise - Introduction to OpenRoad|Overview of the flow | |||
* Exercise - Floorplanning|Floorplanning | |||
* Exercise - Placement / Timing|Placement / Timing | |||
* Exercise - Understanding clock tree|Understanding clock tree | |||
* Exercise - Routing / Finishing|Routing / Finishing | |||
* Exercise - Power analysis|Power analysis | |||
* Exercise - DRC / LVS|DRC / LVS | |||
* Exercise - Tetramax / ATPG|Tetramax / ATPG | |||
* Exercise - Preparing plots, Presenting results|Preparing plots, Presenting results | |||
VLSI Information | Information | |||
* VLSI Projects | Student Projects | |||
* SystemVerilog naming conventions | |||
* Croc |Croc SoC | |||
* VLSI Reading | Further information | |||
* VLSI Contributors | Contributors | |||
Open source IC Design tools | Tools | |||
* Verilator | |||
* Yosys | |||
* OpenROAD | |||
</btn> | </btn> | ||
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[[Category:VLSI]] | [[Category:VLSI]] | ||