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(Created page with "<div class="jumbotron jumbotron-fluid"> <ul> ==Open Source VLSI Design== These pages support the VLSI design activities at [https://www.ethz.ch ETH Zürich] relying on ''mainly'' open source EDA design tools. </ul> </div> ---- ===Code example=== <syntaxhighlight lang="verilog"> module test (input logic data_in_i, input logic clk_ci, input logic rst_ni, output logic [7:0] output_o); // body of module always_f...")
 
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{{VLSInavbar}}
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<div class="jumbotron jumbotron-fluid">
<ul>
<ul>
==Open Source VLSI Design==  
==Open Source VLSI Design==  
These pages support the VLSI design activities at [https://www.ethz.ch ETH Zürich] relying on ''mainly'' open source EDA design tools.
These pages support the VLSI design activities at [https://www.ethz.ch ETH Zürich] relying ''mainly'' on open-source EDA design tools.
</ul>
</ul>
</div>
</div>
----
===Code example===
<syntaxhighlight lang="verilog">
module test (input  logic      data_in_i,
            input  logic      clk_ci,
            input  logic      rst_ni,
            output logic [7:0] output_o);


// body of module
We are in the process of adapting our lecture series using a predominantly open source EDA design flow and an open [[PDK]] from [https://github.com/IHP-GmbH/IHP-Open-PDK IHP].


always_ff (@posedge clk_ci, @negedge rst_ni) begin
<div class="alert alert-danger" role="alert">
  if (rst_ni ==1'b0) begin    //active_low reset
This is still very much work in progress, target is to finish most of it by '''February 2025'''.
    output_o = 8'b0;
</div>
  end else begin
 
    output_o = {8{data_in_i}};
You will find [[VLSI Lectures|lectures]] and [[VLSI Exercises| exercises]] under these pages.
  end
end


endmodule
Open source tools used in these exercises
</syntaxhighlight>
* [[Verilator]]
* [[Yosys]]
* [[OpenROAD]]


Some inline code <code>always_ff</code> or more prominent <kbd>always_comb</kbd>
Other related information
* [[Croc]] a simplified SoC from  [https://github.com/pulp-platform/croc PULP platform] that is being used in all [[VLSI Exercises|exercises]
* [[SystemVerilog naming conventions]]
* [[VLSI Projects|Information on possible student projects]] that forms part of the teaching activity
* [[VLSI Reading| Further references and links]]
{{VLSIfooter}}

Latest revision as of 13:24, 10 October 2024

VLSI
LecturesToggle Dropdown
IntroSystemVerilogSynthesisIC ManufacturingStandard cell based designFloorplanningUnderstanding TimingParasitic effects in VLSI DesignBack-end designPower managementTestingPerformance of ICs
ExercisesToggle Dropdown
Simulation flowBlock diagramsRTL, understanding/extending CrocSynthesisOverview of the flowFloorplanningPlacement / TimingUnderstanding clock treeRouting / FinishingPower analysisDRC / LVSTetramax / ATPGPreparing plots, Presenting results
InformationToggle Dropdown
Student ProjectsSystemVerilog naming conventionsCroc SoCFurther informationContributors
ToolsToggle Dropdown
VerilatorYosysOpenROAD

    Open Source VLSI Design

    These pages support the VLSI design activities at ETH Zürich relying mainly on open-source EDA design tools.

We are in the process of adapting our lecture series using a predominantly open source EDA design flow and an open PDK from IHP.

You will find lectures and exercises under these pages.

Open source tools used in these exercises

Other related information


The VLSI pages are part of the open source VLSI design course offered by the Integrated Systems Laboratory of ETH Zürich, by Luca Benini and Frank K. Gürkaynak. See full list of contributors.

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