VLSI Lectures: Difference between revisions

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(Created page with "{{VLSInavbar}} Synthesis flow, standard cells, memories, drive strengths, basics of timing Steps for IC Design manufacturing, how transistors are made Layers for routing, track width, separation, pitch, standard cell structure, pins Floorplanning, I/O ring, power rings, macros, packages, ESD timing. Setup/hold constraints, prop/cont delay, min/max timing, input output timing, single clock, clock tree, skew, insertion delay, corners Parasitics, extraction, issues in timi...")
 
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Synthesis flow, standard cells, memories, drive strengths, basics of timing
The VLSI2 lecture at [https://www.ethz.ch ETH Zürich] covers aspects of modern digital IC design supported by [[VLSI Exercises]].
Steps for IC Design manufacturing, how transistors are made
Layers for routing, track width, separation, pitch, standard cell structure, pins
Floorplanning, I/O ring, power rings, macros, packages, ESD
timing. Setup/hold constraints, prop/cont delay, min/max timing, input output timing, single clock, clock tree, skew, insertion delay, corners
Parasitics, extraction, issues in timing, crosstalk, noise margins, supply droop, ground bounce
placement/routing, algorithms, filling, antenna, drc, lvs
EASTER BREAK
Power, dynamic/static, glitches, estimation techniques, DVFS, electromigration, IR Drop
Talk about final projects, Q&A
Testing, ATPG, need for test, stuck at faults, JTAG, BIST
Final lecture: Metrics for a good design, efficiency. What we did not cover, future of IC design, trends/technologies
Reserve / Talk about projects
 
=== Schedule ===  
=== Schedule ===  
<table class="table">
<table class="table">
Line 49: Line 36:
   <tr>
   <tr>
       <th scope="row">5</th>
       <th scope="row">5</th>
       <td>[[Lecture - Intro|LEF]]</td>
       <td>[[Lecture - Standard cell based design|LEF]]</td>
       <td>Summary of design flow, cost of IC design, case for open source EDA</td>
       <td>Standard cell structure, routing layers, parasitics </td>
       <td><code>ethz_vlsi_lec1.pptx</code></td>
       <td><code>ethz_vlsi_lec5.pptx</code></td>
     </tr>
     </tr>
   <tr>
   <tr>
       <th scope="row">6</th>
       <th scope="row">6</th>
       <td>[[Lecture - Intro|Intro]]</td>
       <td>[[Lecture - Floorplanning|DEF]]</td>
       <td>Summary of design flow, cost of IC design, case for open source EDA</td>
       <td>Floorplan, I/O ring, ESD structures, packaging</td>
       <td><code>ethz_vlsi_lec1.pptx</code></td>
       <td><code>ethz_vlsi_lec6.pptx</code></td>
     </tr>
     </tr>
   <tr>
   <tr>
       <th scope="row">7</th>
       <th scope="row">7</th>
       <td>[[Lecture - Intro|Intro]]</td>
       <td>[[Lecture - Understanding Timing|LIB]]</td>
       <td>Summary of design flow, cost of IC design, case for open source EDA</td>
       <td>Timing, clock trees, corners</td>
       <td><code>ethz_vlsi_lec1.pptx</code></td>
       <td><code>ethz_vlsi_lec7.pptx</code></td>
     </tr>
     </tr>
   <tr>
   <tr>
       <th scope="row">8</th>
       <th scope="row">8</th>
       <td>[[Lecture - Intro|Intro]]</td>
       <td>[[Lecture - Parasitic effects in VLSI Design|SDF]]</td>
       <td>Summary of design flow, cost of IC design, case for open source EDA</td>
       <td>Parasitics, extraction, issues in timing, crosstalk, noise margins, supply droop, ground bounce</td>
       <td><code>ethz_vlsi_lec1.pptx</code></td>
       <td><code>ethz_vlsi_lec1.pptx</code></td>
     </tr>
     </tr>
   <tr>
   <tr>
       <th scope="row">9</th>
       <th scope="row">9</th>
       <td>[[Lecture - Intro|Intro]]</td>
       <td>[[Lecture - Back-end design|GDS]]</td>
       <td>Summary of design flow, cost of IC design, case for open source EDA</td>
       <td>Placement, routing, chip finishing, DRC/LVS</td>
       <td><code>ethz_vlsi_lec1.pptx</code></td>
       <td><code>ethz_vlsi_lec1.pptx</code></td>
     </tr>
     </tr>
   <tr>
   <tr>
       <th scope="row">10</th>
       <th scope="row">10</th>
       <td>[[Lecture - Intro|Intro]]</td>
       <td>[[Lecture - Power management|VCD]]</td>
       <td>Summary of design flow, cost of IC design, case for open source EDA</td>
       <td>Power analysis, static vs dynamic power, IR drop, analysis methods, DVFS </td>
       <td><code>ethz_vlsi_lec1.pptx</code></td>
       <td><code>ethz_vlsi_lec10.pptx</code></td>
     </tr>
     </tr>
   <tr>
   <tr>
       <th scope="row">11</th>
       <th scope="row">11</th>
       <td>[[Lecture - Intro|Intro]]</td>
       <td>[[Lecture - Testing|WGL]]</td>
       <td>Summary of design flow, cost of IC design, case for open source EDA</td>
       <td>Motivation for test, Fault models, ATPG, BIST, JTAG</td>
       <td><code>ethz_vlsi_lec1.pptx</code></td>
       <td><code>ethz_vlsi_lec11.pptx</code></td>
     </tr>
     </tr>
   <tr>
   <tr>
       <th scope="row">12</th>
       <th scope="row">12</th>
       <td>[[Lecture - Intro|Intro]]</td>
       <td>[[Lecture - Performance of ICs|PPA]]</td>
       <td>Summary of design flow, cost of IC design, case for open source EDA</td>
       <td>Reporting power, performance, area properly</td>
       <td><code>ethz_vlsi_lec1.pptx</code></td>
       <td><code>ethz_vlsi_lec1.pptx</code></td>
     </tr>
     </tr>
  <tr>
      <th scope="row">13</th>
      <td>[[Lecture - Intro|Intro]]</td>
      <td>Summary of design flow, cost of IC design, case for open source EDA</td>
      <td><code>ethz_vlsi_lec1.pptx</code></td>
    </tr>
  </table>
  </table>
{{VLSIfooter}}
{{VLSIfooter}}

Latest revision as of 08:37, 9 August 2024

VLSI
LecturesToggle Dropdown
IntroSystemVerilogSynthesisIC ManufacturingStandard cell based designFloorplanningUnderstanding TimingParasitic effects in VLSI DesignBack-end designPower managementTestingPerformance of ICs
ExercisesToggle Dropdown
Simulation flowBlock diagramsRTL, understanding/extending CrocSynthesisOverview of the flowFloorplanningPlacement / TimingUnderstanding clock treeRouting / FinishingPower analysisDRC / LVSTetramax / ATPGPreparing plots, Presenting results
InformationToggle Dropdown
Student ProjectsSystemVerilog naming conventionsCroc SoCFurther informationContributors
ToolsToggle Dropdown
VerilatorYosysOpenROAD

The VLSI2 lecture at ETH Zürich covers aspects of modern digital IC design supported by VLSI Exercises.

Schedule

Lecture Name Topics Slides
1 Intro Summary of design flow, cost of IC design, case for open source EDA ethz_vlsi_lec1.pptx
2 RTL Refresher on SystemVerilog, a few words on computer architecture, our example design Croc ethz_vlsi_lec2.pptx
3 Netlist Logic synthesis, standard cells, other macros, refresher on timing ethz_vlsi_lec1.pptx
4 ICT Short summary of IC manufacturing ethz_vlsi_lec4.pptx
5 LEF Standard cell structure, routing layers, parasitics ethz_vlsi_lec5.pptx
6 DEF Floorplan, I/O ring, ESD structures, packaging ethz_vlsi_lec6.pptx
7 LIB Timing, clock trees, corners ethz_vlsi_lec7.pptx
8 SDF Parasitics, extraction, issues in timing, crosstalk, noise margins, supply droop, ground bounce ethz_vlsi_lec1.pptx
9 GDS Placement, routing, chip finishing, DRC/LVS ethz_vlsi_lec1.pptx
10 VCD Power analysis, static vs dynamic power, IR drop, analysis methods, DVFS ethz_vlsi_lec10.pptx
11 WGL Motivation for test, Fault models, ATPG, BIST, JTAG ethz_vlsi_lec11.pptx
12 PPA Reporting power, performance, area properly ethz_vlsi_lec1.pptx


The VLSI pages are part of the open source VLSI design course offered by the Integrated Systems Laboratory of ETH Zürich, by Luca Benini and Frank K. Gürkaynak. See full list of contributors.

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