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8 August 2024

6 August 2024

5 August 2024

17 July 2024

  • 15:0915:09, 17 July 2024 diff hist −12 VLSINo edit summary
  • 15:0915:09, 17 July 2024 diff hist +689 VLSINo edit summary
  • 14:5414:54, 17 July 2024 diff hist +18 VLSINo edit summary
  • 14:5414:54, 17 July 2024 diff hist +760 N VLSICreated page with "<div class="jumbotron jumbotron-fluid"> <ul> ==Open Source VLSI Design== These pages support the VLSI design activities at [https://www.ethz.ch ETH Zürich] relying on ''mainly'' open source EDA design tools. </ul> </div> ---- ===Code example=== <syntaxhighlight lang="verilog"> module test (input logic data_in_i, input logic clk_ci, input logic rst_ni, output logic [7:0] output_o); // body of module always_f..."

15 July 2024

8 October 2023

14 June 2023

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