VLSI

Open Source VLSI Design

These pages support the VLSI design activities at ETH Zürich relying on mainly open source EDA design tools.

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Code example

module test (input  logic       data_in_i,
             input  logic       clk_ci,
             input  logic       rst_ni,
             output logic [7:0] output_o);

// body of module 

always_ff (@posedge clk_ci, @negedge rst_ni) begin
  if (rst_ni ==1'b0) begin    //active_low reset 
    output_o = 8'b0;
  end else begin
    output_o = {8{data_in_i}};
  end 
end

endmodule

Some inline code always_ff or more prominent always_comb